1. Field of the Invention
The present invention relates to an integrated semiconductor device having a plurality of connection levels, and a manufacturing method thereof.
2. Description of the Related Art
As known, the integration of semiconductor devices is always and always increasing, because of the progresses in the semiconductor technology. In particular, the availability of a plurality of metal layers for interconnections has been decisive in making the signal routing more compact.
In devices having a plurality of connection levels (layers of metal or another conductive material), electrical connections exist between connection regions formed in successive connection levels, and between connection levels formed in the first connection level and regions integrated in the device substrate; these connections are formed by through regions (plugs or contacts) extending through the insulating material separating the various connection levels from one another, and from the integrated regions of the device. In addition, connections are sometimes present between connection regions belonging to non-consecutive connection levels, for example between an (Nxe2x88x921)-th metal layer and an (N+1)-th metal layer, or between integrated regions and connection regions that do not belong to the first metal level. In this case, now, it is necessary to form intermediate regions or islands in the intermediate connection layer (for example the N-th metal layer).
An example of connection between a connection region formed in the third level (third metal layer) and a connection region formed in the first level (first metal layer) is shown in FIGS. 1a and 1b, which show respectively a top plan view and a cross-section of a device 1. The device 1 comprises a substrate 3 of a first conductivity type (for example P), accommodating an integrated region 4 of a second conductivity type (for example N). On substrate 1 there extend in succession a first dielectric layer 5, a first metal level 6, a second dielectric layer 7, a second metal level 10, a third dielectric layer 9, and a third metal level 11.
The first metal layer 6 comprises a first connection region 6a; the second metal layer 10 comprises second connection regions 10a, and the third metal layer 11 comprises a third connection region 11a. The first connection region 6a is connected to the integrated region 4 by a contact 12, which extends through the first dielectric layer 5; in addition, the first connection region 6a is connected to the third connection region 11a by an intermediate region or xe2x80x9cislandxe2x80x9d 10b, which is formed in the second metal level 10. The intermediate island 10b is connected to the first connection region 6a by a first plug 15 passing through the second dielectric layer 7, and it is connected to the third connection region 11a by a second plug 16 passing through the third dielectric layer 9.
The manufacture of the intermediate island 10b involves a certain bulk, since it is necessary to comply with rules regarding the width of the intermediate island (which is therefore wider than plugs 15, 16), and the minimum distance from the regions (connection regions 10b) formed on the same metal level. It is apparent that when different connections must be provided between connection and/or integrated regions belonging to non-adjacent levels, this results in a considerable spatial dimension. In addition, sometimes, the space required by the intermediate islands does not allow the device layout to be optimized. This is the case for example of non-volatile EPROM, EEPROM and flash-EEPROM memories, wherein it is required to connect all, or a large number, of polysilicon control gate regions on the first metal level (xe2x80x9cword line strapxe2x80x9d), and the drain regions on the same bit line on the second metal level to reduce the capacitive connection between the second metal level and the substrate, and thus the parasitic capacities.
An object of the invention is to provide a solution allowing a reduction in the space necessary for connecting two connection regions, or a connection region and an integrated region of the device, arranged on non-consecutive levels.
According to principles of the present invention, an integrated semiconductor device having a plurality of connections levels and a manufacturing method thereof are provided.
To help understanding of the present invention, preferred embodiments are now described, purely by way of non-limiting example, with reference to the attached drawings.